Artur Jutman

Researches

  1. Centre for Trustworthy and Efficient Computing Hardware (TECH)

Publications

NURSE: A Distributed Architecture for Runtime Fault Management in Processor Designs
Authors: Santhosh, Ashwin; Jutman, Artur; Kaja, Endri; Ecker, Wolfgang; Jenihhin, Maksim
Year: 2026
Special Session: Reliability Assessment of DNN Models and Inference on Systolic Arrays
Journal / Periodical: Proceedings of the IEEE VLSI Test Symposium
Authors: Cherezova, N.; Pappalardo, S.; Ruospo, A.; Deveautour, B.; Fezza, L.; Jutman, A.; Sanchez, E.; Bosio, A.; Reorda, M.S.; Jenihhin, M.
Year: 2026
European Test Symposium Teams: an Anniversary Snapshot
Journal / Periodical: 2025 IEEE European Test Symposium (ETS)
Authors: Jenihhin, M.; Raik, J.; Jutman, A.; Cherezova, N.; Ubar, R.; Miclea, L.; Enyedi, S.; Stefan, I.; Stan, O.; Corches, C.; Peng, Z.; Eles, P.; Drechsler, R.; Eggersgluss, S.; Fey, G.; Glowatz, A.; Tille, D.; Gielen, G.; Coyette, A.; Dobbelaere, W.; Vanhooren, R.; Chuang, P. -Y.; Marinissen, E. J.; Di Natale, G.; Barragan, M.; Maistri, P.; Mir, S.; Vatajelu, E. -I.; Bernardi, P.; Di Carlo, S.; Prinetto, P.; Reorda, M. Sonza; Violante, M.; Stratigopoulos, H. -G.; Michael, M. K.; Neophytou, S.; Hadjitheophanous, S.; Christou, K.; Skitsas, M.; Bosiol, A.; Deveautour, B.; Girard, P.; Traiolan, M.; Virazel, A.; dos Santos, E. Fernandes; Kritikakou, A.; Casagranda, G.; Vallero, M.; Vella, F.; Rech, P.; Poehls, L. M. Bolzani; Krstic, M.; Andjelkovic, M.; Vargas, F.; Tshagharyan, G.; Harutyunyan, G.; Vardanian, V.; Shoukourian, S.; Zorian, Y.; Dworak, J.; Nepal, K.; Manikas, T.; Taoui, M.; Fieback, M.; Gebregiorgis, A.; Bishnoi, R.; Hamdioui, S.; Chatterjee, A.; Saha, A.; Komarraju, S.; Ma, K.; Amarnath, C.; Tahoori, M.; Mayahinia, M.; Rajabalipanah, M.; Basharkhah, K.; Nosrati, N.; Jahanpeima, Z.; Navabi, Z.; Wunderlich, H. -J.; Hellebrand, S.
Year: 2025

Projects

European Spallation Source
Year: 2025 - 2029
Design, implementation and validation of Scalable PARametrizable Kernels for cost-effective AI accelerator CHIPs (SPARK-CHIP)
Year: 2026 - 2029
The overall aim of the Thematic R&D Programme project SPARK-CHIP is to strengthen the R&D capacity, training and cooperation in TalTech and TKK School of Applied Sciences and to foster business-oriented R&D collaboration with Electronics Industry Association and Metrosert Chip Centre in the field of AI chip design. The scientific scope of the project is defined in close cooperation with two innovative Estonian technology companies: Skeleton and Imaginal Microsystems that will monitor the progress of R&D within the project. The project aims at development of a novel platform for cost-effective parametrizable and reliable system-on-chip cores for AI accelerators, supporting emerging AI models and validating it in real silicon. The research builds on TalTech’s previous results in the area of reliable AI chips design and it contributes to advancing the Estonian ICT hardware ecosystem by gaining strategic knowledge on AI deployment on hardware as well as on chip design and production.
Training and Innovation in Reliable and Efficient Chip Design for Edge AI
Year: 2024 - 2028
TIRAMISU “Training and Innovation in Reliable and Efficient Chip Design for Edge AI” is a European HORIZON MSCA Doctoral Network project. The general research objective of TIRAMISU is a practical methodology for reliable and energy-efficient Edge AI hardware backbone design and innovation management. The action will provide strong interdisciplinary training for future European engineers and researchers driving the innovation for reliable and energy-efficient Edge AI chips. The consortium is strategically designed to foster cross-disciplinary synergies, by seamlessly integrating innovation management research with the technical aspects of Edge AI design. The non-academic sector is represented by a European flagship R&D hub for nanoelectronics - IMEC, a global leader in industrial electronics and the largest semiconductor manufacturer in Germany - Infineon, a trusted automotive solutions provider - Dumarey, the worldwide leader in EDA tools development - Cadence. The academic excellence is established by the top ICT and Technology Innovation engineering universities and Europe's largest application-oriented research organisation - Fraunhofer.