Projects

TIRAMISU “Training and Innovation in Reliable and Efficient Chip Design for Edge AI” is a European HORIZON MSCA Doctoral Network project. The general research objective of TIRAMISU is a practical methodology for reliable and energy-efficient Edge AI hardware backbone design and innovation management. The action will provide strong interdisciplinary training for future European engineers and researchers driving the innovation for reliable and energy-efficient Edge AI chips. The consortium is strategically designed to foster cross-disciplinary synergies, by seamlessly integrating innovation management research with the technical aspects of Edge AI design. The non-academic sector is represented by a European flagship R&D hub for nanoelectronics - IMEC, a global leader in industrial electronics and the largest semiconductor manufacturer in Germany - Infineon, a trusted automotive solutions provider - Dumarey, the worldwide leader in EDA tools development - Cadence. The academic excellence is established by the top ICT and Technology Innovation engineering universities and Europe's largest application-oriented research organisation - Fraunhofer.

Reinforcing Skills in Chips Design for Europe (RESCHIP4EU) aims to support the excellence of EU higher education in the area of embedded systems design in a holistic way, from silicon via System-on-Chip design and manufacturing to smart and safety-critical platform and application software. The holistic nature of the program is essential for innovation and provides a unique competitive edge to program graduates to design, analyse and innovate smart, green and safety-critical embedded systems in Europe. RESCHIP4EU will achieve this goal by designing and delivering a double-degree master’s programme (ISCED Level 7, 120 ECTS) in Embedded Systems Design with several specialisations related to the holistic design of embedded platforms safer, greener, smarter, and more efficient and a minor in Innovation and Entrepreneurship. The master’s programme will be designed and delivered by 9 higher education institutions from 5 different countries with the collaboration of Semi.org, the global industry association representing the electronics manufacturing and design supply chain, ST Microelectronics, a global semiconductor company, 1 innovative SME expert in delivering education program, communication and dissemination, 1 ASBL (Association internationale sans but lucrative), and EIT Digital, a pan-European organisation with experience in delivering education programmes in advanced digital skills across Europe.

Building on TalTech’s expertise in the field of computer engineering and its high-level capacity in the domain of diagnostics and testing of nanoelectronic systems, this project aims at establishing in TalTech, with the strong support of the Advanced Partners, the capacity to R&D&I a complete customised AI-chip design flow. The research ambition of the TAICHIP (TalTech AI-chip) action is a leading-edge forward-thinking R&D framework for reliable and resource-efficient custom AI-chips based on open HW architectures (e.g., RISC-V, NVDLA), open EDA (Electronic Design Automation) tools, methodologies and implementation technologies satisfying the requirements of AI applications of tomorrow. TAICHIP project also allows building at TalTech the necessary scientific knowledge, research skills, administrative and management skills, as well as strengthening its advanced training and education capacity. Evenly related to the central goal are the additional measures that focus on building the supporting capacities, as well as dissemination, exploitation and communication, and public policy focused activities.

The objective of this collaborative project is to enable trustworthy AI hardware by explainable and efficient Deep Neural Networks. As the main contribution to achieving this objective, the project will establish an EnTrustED Framework for DNN hardware design analysis that will follow the novel design flow. First, at the design-time phase, a combination of DNN-tailored AxC techniques will be provided to enhance the compute-efficiency of the DNN inference hardware. The Framework will enable a simulation-based analysis for identifying the neurons that are not practical for the optimisation and must keep their initial Exact Computing (ExC) implementation or the approximation should be reduced. It aims to equip the AI hardware with self-test mechanisms to detect hardware errors and fault-tolerance mechanisms for recovering from an error that has occurred and, thereby, continue the AI algorithm uninterruptedly. As one of the novelties, this project views eXplainable AI (XAI) from a hardware perspective. We intend to consider the AxC during the explainability and thus ensure a correct explanation of the decision taken by the DNN. Once we guarantee the correct behaviour of the hardware, and we have properly considered AxC, we can safely run explainability approaches to profile the DNN implantation still at the design-time for identification of DNN input specific significant neurons. The experimental nature of the project and the high interdependency of the contributions by EC-Lyon and TalTech make the envisioned face-to-face visits essential to achieving the goals of the collaboration.